1. Field of the Invention
The present invention relates to a transistor, a semiconductor memory comprising the same and a method of fabricating the same.
2. Description of the Related Art
Nonvolatile semiconductor memories such as a ferroelectric random access memory, an EPROM (erasable and programmable read only memory), an EEPROM (electrically erasable and programmable read only memory) and the like have been recently considered.
A memory cell (memory transistor) of an EPROM or an EEPROM stores charges in a floating gate electrode for storing data in response to presence/absence of the charges while sensing change of a threshold voltage resulting from presence/absence of charges for reading the data. In particular, the EEPROM includes a flash EEPROM entirely erasing data in a memory cell array or dividing the memory cell array into arbitrary blocks for erasing data in units of the blocks.
Memory cells forming the flash EEPROM are roughly classified into a stacked gate memory cell and a split gate memory cell.
In the stacked gate memory cell, a source region and a drain region are formed on a silicon substrate and a floating gate electrode in an electrically floating state is formed on a channel region held between the source region and the drain region through a silicon oxide film. A control gate electrode is formed on the floating gate electrode through a silicon oxide film.
The floating gate electrode and the control gate electrode are identical in size to each other along the direction of the channel length, and stacked with each other with no misalignment. The control gate electrode is extended in a direction perpendicular to that of the channel length to be common to a plurality of floating gate electrodes, for forming a word line.
The flash EEPROM employing stacked gate memory cells having the aforementioned structure has no function of selecting each memory cell itself. If charges are excessively extracted from the floating gate electrode for erasing data, therefore, such a problem of overerasing is caused that the memory cell regularly enters an ON state (conducting state) and is broken.
In order to prevent overerasing, the erasing procedure must be controlled in a peripheral circuit or an external circuit for the memory device.
The split gate memory cell has been developed in order to solve the problem of overerasing in the stacked gate memory cell. For example, U.S. Pat. No. 5,029,130, WO92/18980 (G11C 13/001 3/00) or the like discloses a flash EEPROM employing split gate memory cells.
FIG. 70 is a sectional view of a conventional split gate memory cell 200. Referring to FIG. 70, a source region 202 and a drain region 203 are formed on a surface of a silicon substrate 201 at a prescribed space. A floating gate electrode 206 is formed on a channel region 204 held between the source region 202 and the drain region 203 through a first insulator film 205 of silicon oxide. A control gate electrode 208 is formed on the floating gate electrode 206 through a second insulator film 207 of silicon oxide.
The source region 202, the drain region 203, the channel region 204, the first insulator film 205, the floating gate electrode 206, the second insulator film 207 and the control gate electrode 208 form the split gate memory cell (split gate transistor) 200.
A part of the control gate electrode 208 is arranged on the channel region 204 through an insulator film 209 of silicon oxide. The part of the control gate electrode 208 located on the channel region 204 forms a selection gate electrode 210. The selection gate electrode 210, the source region 202, the drain region 203 and the channel region 204 form a selection transistor 211 for selecting the memory cell 200 itself.
In other words, the split gate memory cell 200 has such a structure that a transistor formed by the gate electrodes 206 and 208 and the regions 202, 203 and 204 and the selection transistor 211 are serially connected with each other.
The split gate memory cell 200 having the aforementioned structure has a function of selecting itself with the selection transistor 211. Even if overerasing takes place, therefore, the selection transistor 211 can control conduction and non-conduction of the memory cell 200, to cause no problem.
A write operation and an erase operation in the split gate memory cell 200 are now described with reference to FIG. 71 and FIG. 72, respectively.
In data writing, the potential of the drain region 203 is set at 0 V, a high voltage exceeding 10 V is applied to the source region 202, and a voltage of about several V is applied to the control gate electrode 208, as shown in FIG. 71. Thus, the selection transistor 211 is turned on so that electrons travel from the drain region 203 to the source region 202.
At this time, the potential of the floating gate electrode 206, which is capacitively coupled with the source region 202 through the first insulator film 205 and with the control gate electrode 208 through the second insulator film 207, increases to about 10 V, i.e., a value close to the potential of the source region 202. Therefore, the electrons travelling through the channel region 204 are attracted by the floating gate electrode 206 and injected into the same beyond a potential barrier of the first insulator film 205 as hot electrons.
When the floating gate electrode 206 thus stores electrons, no channel is formed on the channel region 204 located under the floating gate electrode 206 and no cell current flows even if a positive voltage is applied to the control gate electrode 208. This state is called a write state, in which the memory cell 200 stores data xe2x80x9c0xe2x80x9d.
In data erasing, the potentials of both of the source region 202 and the drain region 203 are set at 0 V and a high voltage exceeding 10 V is applied to the control electrode 208, as shown in FIG. 72. In this case, the potential of the floating gate electrode 206, which is capacitively coupled with the source region 202 through the first insulator film 205 and with the control gate electrode 208 through the second insulator film 207, reduces to about several V, i.e., a value close to the potential of the source region 202. Thus, potential difference of about 10 V is caused between the floating gate electrode 206 and the control gate electrode 208.
Consequently, electrons stored in the floating gate electrode 206 are extracted to the control gate electrode 208 through the second insulator film 207 as a Fowler-Nordheim tunnel current (hereinafter referred to as an F-N tunnel current).
When a positive voltage is applied to the control gate electrode 208 while the electrons are extracted from the floating gate electrode 206 as described above, a channel is formed on the channel region 204 located under the control gate electrode 206 and a cell current flows. This state is called an erase state, in which the memory cell 202 stores data xe2x80x9c1xe2x80x9d.
At this time, the electrons jump out from a projection 206a formed on the floating gate electrode 206 and move toward the control gate electrode 208. Thus, movement of the electrons is so facilitated that the electrons can be efficiently extracted from the floating gate electrode 206.
A method of fabricating such a split gate memory cell is disclosed in U.S. Pat. No. 5,045,488, for example. A thin oxide film is formed on the semiconductor substrate 201 and a polysilicon film for forming the floating gate electrode 206 is deposited on the thin oxide film. Thereafter a silicon nitride film is stacked on the polysilicon film and an opening is formed in a portion of the silicon nitride film for forming the floating gate electrode 206.
Further, the polysilicon film exposed on the opening of the silicon nitride film is oxidized in an oxidizing atmosphere, for forming an oxide film of polysilicon in the opening. Further, the remaining silicon nitride film is removed and the polysilicon film is etched through the oxide film of polysilicon serving as a mask, thereby forming the floating gate electrode 206.
However, it is difficult to highly integrate the aforementioned split gate memory cell 200 as compared with the stacked gate memory cell, as described below:
In the stacked gate memory cell, the floating gate electrode and the control gate electrode, which are identical in width to each other, are stacked with each other with no misalignment. In the split gate memory cell 200, on the other hand, a part of the control gate electrode 208 is arranged on the channel region 204 to form the selection gate electrode 210. In the split gate memory cell 200, therefore, the area occupied by the element on the silicon substrate 201 is increased by the selection gate electrode 210 as compared with the stacked gate memory cell. In other words, it is difficult to highly integrate the split gate memory cell 200, although no problem of overerasing takes place.
FIG. 73(a) is a sectional view of the conventional split gate memory cell shown in FIG. 70 taken along the line Exe2x80x94E in FIG. 73(b), FIG. 73(b) is a plan view of the split gate memory cell, and FIG. 73(c) is a sectional view taken along the line.
FIG. 73(a) is a sectional view of the conventional split gate memory cell shown in FIG. 70 taken along the line Exe2x80x94E in FIG. 73(b), FIG. 73(b) is a plan view of the split gate memory cell, and FIG. 73(c) is a sectional view taken along the line Fxe2x80x94F FIG. 73(b), respectively.
In the write operation shown in FIG. 71, the potential of the floating gate electrode 206, which is decided by the ratio of the coupling capacitance C1 between the source electrode 202 and the floating gate electrode 206 to the coupling capacitance C2 between the floating gate electrode 206 and the control gate electrode 208, is increased as the ratio of the coupling capacitance C1 to the coupling capacitance C2 is increased.
As hereinabove described, the floating gate electrode 206 and the control gate electrode 208 form the electric capacitance through three surfaces, to increase the coupling capacitance C2 therebetween. Consequently, it is difficult to inject electrons from the channel region 204 into the floating gate electrode 206 at a high speed, and the speed of the write operation is reduced.
A word line defined by the control gate electrode 208 is formed on the silicon substrate 201 through a field isolation film 213, as shown in FIGS. 73(b) and 73(c). Thus, a wiring capacitance is formed between the control gate electrode 208 and the silicon substrate 201. This wiring capacitance delays a signal on the control gate electrode 208.
FIG. 74 is a sectional view showing another conventional split gate memory cell 701.
The split gate memory cell (split gate transistor) 701 is formed by a source region 703, a drain region 704, a channel region 705, a floating gate electrode 706 and a control gate electrode 707.
The n-type source and drain regions 703 and 704 are formed on a p-type single-crystalline silicon substrate 702. The floating gate electrode 706 is formed on the channel region 705 held between the source region 703 and the drain region 704 through a gate isolation film 708. An insulator film 709 and a tunnel isolation film 710 are formed on the floating gate electrode 706 by a LOCOS (local oxidation of silicon) method, and the control gate electrode 707 is formed on the tunnel isolation film 710. The insulator film 709 forms a projection 706a on the floating gate electrode 706.
A part of the control gate 707 is arranged on the channel region 705 through the isolation films 708 and 710, to form a selection gate 711. The selection gate 711 and the source and drain regions 703 and 704 form a selection transistor 712. In other words, the split gate memory cell 701 has such a structure that a transistor formed by the gate electrodes 706 and 707 and the regions 703 and 704 and the selection transistor 712 are serially connected with each other.
FIGS. 75(a) and 75(b) show a memory cell array 802 of a flash EEPROM employing a plurality of such split gate memory cells 701. FIG. 75(b) is a partially fragmented plan view of the memory cell array 802, and FIG. 75(a) is a sectional view taken along the line Xxe2x80x94X in FIG. 75(b).
The memory cell array 802 is formed by the plurality of memory cells 701 formed on the p-type single-crystalline silicon substrate 702. In order to reduce the occupied area on the substrate 702, each pair of memory cells 701 (hereinafter denoted by 701a and 701b) share each source region 703 in common, and the floating gate electrodes 706 and the control gate electrodes 707 thereof are arranged to be line-symmetrical to each other about the common source region 703.
Field isolation films 713 are formed on the substrate 702 for isolating the memory cells 701 from each other. The memory cells 701 vertically arranged in FIG. 75(b) share the source regions 703 in common. Further, the memory cells 701 vertically arranged in FIG. 75(b) also share the control gate electrodes 707 in common, and these control gate electrodes 707 form word lines. On the other hand, the drain regions 704 transversely arranged in FIG. 75(b) are connected to bit lines (not shown) through bit line contacts 714.
Operation modes (write, read and erase operations) of the flash EEPROM are now described with reference to FIGS. 76(a), 76(b) and 76(c).
The drain region 704 of a selected memory cell 701 is connected to a constant current source 810a provided in a sense amplifier 810, so that its potential is set at 1.2 V. The potentials of the drain regions 704 of the remaining memory cells 701 are set at 3 V.
The potential of the control gate electrode 707 of the selected memory cell 701 is set at 2 V. The potentials of the control gate electrodes 707 of the remaining memory cells 701 are set at 0 V.
The potentials of the source regions 703 of all memory cells 701 are set at 12 V.
In each memory cell 701, the threshold voltage Vth of the selection transistor 712 is about 0.5 V. In the selected memory cell 701, therefore, electrons in the drain region 704 move to the channel region 705, which is in an inverted state. Thus, a cell current flows from the source region 703 toward the drain region 704. The potential of the source region 703 is 12 V, and hence the potential of the floating gate electrode 706 is pulled up to be close to 12 V due to coupling through the electrostatic capacitance between the source region 703 and the floating gate electrode 706. Thus, a high electric field is formed between the channel region 705 and the floating gate electrode 706. Therefore, the electrons in the channel region 705 are accelerated to form hot electrons, which in turn are injected into the floating gate electrode 706 as shown by arrow A in FIG. 76(a). Consequently, charges are stored in the floating gate electrode 706 of the selected memory cell 701 so that 1-bit data is written and stored therein.
This write operation can be performed every selected memory cell 701.
The potential of the drain region 704 of the selected memory cell 701 is set at 2 V. The potentials of the drain regions 704 of the remaining memory cells 701 are set at 0 V.
The potential of the control gate electrode 707 of the selected memory cell 701 is set at 4 V. The potentials of the control gate electrodes 707 of the remaining memory cells 701 are set at 0 V.
The potentials of the source regions 703 of all memory cells 701 are set at 0 V.
As described later, the floating gate electrode 706 of a memory cell 701 which is in an erase state stores no charges. On the other hand, the floating gate electrode 706 of a memory cell 701 which is in a write state stores charges, as described above. Therefore, the channel region 705, located immediately under the floating gate electrode 706, of the memory cell 701 in the erase state is in an ON state, while the channel region 705, located immediately under the floating gate electrode 706, of the memory cell 701 in the write state is close to an OFF state. When a voltage of 4 V is applied to the control gate electrode 707, therefore, a larger cell current flows from the drain region 704 toward the source region 703 in the memory cell 701 in the erase state, as compared with that in the write state.
The value of the data stored in the memory cell 701 can be read by determining the values of the cell currents flowing in the memory cells 701 with the sense amplifier 810. For example, the value of the data in the memory cell 701 of the erase state is set at xe2x80x9c1xe2x80x9d and that of the data in the memory cell 701 of the write state is set at xe2x80x9c0xe2x80x9d for performing the read operation. In other words, the data values xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d in the erase and write states can be stored in the memory cells 701 for reading the data values.
The potentials of the drain regions 704 of all memory cells 701 are set at 0 V.
The potential of the control gate electrode 707 of the selected memory cell 701 is set at 15 V. The potentials of the control gate electrodes 707 of the remaining memory cells 701 are set at 0 V.
The potentials of the source regions 703 of all memory cells 701 are set at 0 V.
The electrostatic capacitance between the source region 703 and the substrate 702 and the floating gate electrode 706 is extremely larger than that between the control gate electrode 707 and the floating gate electrode 706. In other words, the floating gate electrode 706 is strongly coupled with the source region 703 and the substrate 702. Even if the potentials of the control gate electrode 707 and the drain region 704 reach 15 V and 0 V respectively, therefore, the potential of the floating gate electrode 706 substantially remains around 0 V and the potential difference between the control gate electrode 707 and the floating gate electrode 706 is increased to form a high electric field between these electrodes 707 and 706.
Consequently, a Fowler-Nordheim tunnel current (hereinafter referred to as an F-N tunnel current) flows to extract electrons in the floating gate electrode 706 toward the control gate electrode 707 as shown by arrow in FIG. 76(c), for erasing data stored in the memory cell 701.
At this time, the electrons in the floating gate electrode 706 jump from the projection 706a formed thereon and move toward the control gate electrode 707. Thus, movement of the electrons is so facilitated that the electrons can be efficiently extracted from the floating gate electrode 706.
The control gate electrodes 707 of the memory cells 701 arranged along the row direction form common word lines. Therefore, the erase operation is performed on all memory cells 701 connected to a selected word line.
A plurality of word lines can be simultaneously selected for erasing data from all memory cells 701 connected thereto. An erase operation of dividing the memory cell array 802 into arbitrary blocks for a plurality of sets of word lines and erasing data in units of the blocks is called block erasing.
In the flash EEPROM employing the split gate memory cells 701 having the aforementioned structure, each memory cell 701 has a function of selecting itself due to the selection transistor 712. Even if charges are excessively extracted from the floating gate electrode 706 for erasing data, the selection gate 711 can bring the channel region 705 into an OFF state. Even if overerasing takes place, therefore, the selection transistor 712 can control the ON/OFF state of the memory cell 701 and the overerasing causes no problem. In other words, the selection transistor 712 provided in the memory cell 701 can select the ON/OFF state of the memory cell 701 itself.
A method of fabricating the memory cell array 802 is now described in order.
(1) Step 1 (see FIG. 77(a))
The field isolation films 713 (not shown) are formed on the substrate 702 by LOCOS. Then, the gate isolation film 708 of silicon oxide is formed on portions (element regions) of the substrate 702 provided with no field isolation films 713 by thermal oxidation. Then, a doped polysilicon film 715 for defining the floating gate electrodes 706 is formed on the gate isolation film 708. Then, a silicon nitride film 716 is formed on the overall surface of the doped polysilicon film 715 by LPCVD (low-pressure chemical vapor deposition). Then, a photoresist is applied to the overall surface of the silicon nitride film 716 and thereafter an etching mask 717 for defining the floating gate electrodes 706 is formed by general photolithography.
(2) Step 2 (see FIG. 77(b))
The silicon nitride film 716 is anisotropically etched through the etching mask 717. Then, the etching mask 717 is removed. Then, the doped polysilicon film 715 is oxidized by LOCOS through the etched silicon nitride film 716 serving as an oxidation mask, thereby forming the insulator films 709. At this time, ends of the insulator films 709 enter end portions of the silicon nitride film 716, to form bird""s beaks 709a. 
(3) Step 3 (see FIG. 77(c))
The silicon nitride film 716 is removed. Then, the doped polysilicon film 715 is anisotropically etched through the insulator films 709 serving as etching masks, for forming the floating gate electrodes 706. At this time, upper edge portions of the floating gate electrodes 706 sharpen along the shapes of the bird""s beaks 709a formed on the end portions of the insulator films 709, to form the projections 706a. 
(4) Step 4 (see FIG. 77(d))
The tunnel isolation film 710 of silicon oxide is formed on the overall surface of the device formed in the aforementioned step by thermal oxidation and/or LPCVD. Thus, the stacked isolation films 708 and 710 and the stacked insulator and isolation films 709 and 710 are integrated with each other respectively.
(5) Step 5 (see FIG. 78(e))
A doped polysilicon film 718 for defining the control gate electrodes 707 is formed on the overall surface of the device formed in the aforementioned step.
(6) Step 6 (see FIG. 78(f))
A photoresist is applied to the overall surface of the device formed in the aforementioned step, and thereafter an etching mask 719 for defining the control gate electrodes 707 is formed by general photolithography.
(7) Step 7 (see FIG. 78(g))
The doped polysilicon film 718 is anisotropically etched through the etching mask 719 for forming the control gate electrodes 707. Thereafter the etching mask 719 is removed.
(8) Step 8 (see FIG. 79(h))
A photoresist is applied to the overall surface of the device formed in the aforementioned step and thereafter an ion implantation mask 720 for defining the source regions 703 is formed by general photolithography. Then, phosphorus ions (P+) are injected into the surface of the substrate 702 by general ion implantation for forming the source regions 703. Thereafter the ion implantation mask 720 is removed.
At this time, the ion implantation mask 720 is so formed as to cover at least portions of the substrate 702 for forming the drain regions 704 while not jutting out from the floating gate electrodes 706. Consequently, end portions of the floating gate electrodes 706 define the positions of the source regions 703.
(9) Step 9 (see FIG. 79(i))
A photoresist is applied to the overall surface of the device formed in the aforementioned step and thereafter an ion implantation mask 721 for defining the drain regions 704 is formed by general photolithography. Then, arsenic ions (As+) are injected into the surface of the substrate 702 by general ion implantation for forming the drain regions 704.
At this time, the ion implantation mask 721 is so formed as to cover at least the source regions 703 while not jutting out from the control gate electrodes 707. Consequently, end portions of the control gate electrodes 707 closer to the selection gates 711 define the positions of the drain regions 704.
Then, the ion implantation mask 721 is removed for completing the memory cell array 802.
However, the flash EEPROM employing the aforementioned split gate memory cells 701 has the following problems:
(1) The write characteristics of the memory cells 701 are dispersed due to misalignment of the etching mask 719 for forming the control gate electrodes 707.
(1) If the position of the etching mask 719 for forming the control gate electrodes 707 is misaligned with respect to the memory cells 701a and 701b in the step 6 as shown in FIG. 80(a), the control gate electrodes 707 of the memory cells 701a and 701b are formed in shapes different from each other in the step 7.
In formation of the drain regions 704 by ion implantation in the step 9, the end portions of the control gate electrodes 707 closer to the selection gates 711 define the positions of the drain regions 704.
When the position of the etching mask 719 is misaligned as shown in FIG. 80(a), therefore, the lengths (channel lengths) L1 and L2 of the channel regions 705 of the memory cells 701a and 701b differ from each other, as shown in FIG. 80(b). When the position of the etching mask 719 is misaligned toward the memory cell 701b, for example, the channel length L2 of the memory cell 701b is smaller than the channel length L1 of the memory cell 701a. 
When the channel lengths L1 and L2 are different from each other, the channel regions 705 are also different in resistance from each other and hence the values of cell currents flowing in the write operation differ from each other. As the channel length is increased, the resistance of each channel region 705 is increased and the cell current flowing in the write operation is reduced. When the values of the cell currents flowing in the write operation differ from each other, the rates of generation of hot electrons also differ from each other. Consequently, the memory cells 701a and 701b have different write characteristics.
(2) Refinement of the memory cells 701 is inhibited due to avoidance of the aforementioned problem (1).
When designing the split gate memory cell 701, the positional relation between the gate electrodes 706 and 707 and the regions 703 and 704 must previously be set with allowance in consideration of not only dimensional accuracy of worked line widths of the gate electrodes 706 and 707 but also superposition dimensional accuracy of the gate electrodes 706 and 707. When working a thin line of about 0.5 xcexcm in width through a recent semiconductor refinement technique, however, obtained superposition dimensional accuracy is only about 0.1 to 0.2 xcexcm, although dimensional accuracy for the worked line width is obtained up to about 0.05 xcexcm. In other words, refinement of the split gate memory cell 701 is hindered due to the low superposition dimensional accuracy for the gate electrodes 706 and 707.
(3) The split gate memory cell 701 is hard to refine as compared with the stacked gate memory cell.
In the stacked gate memory cell, the floating gate electrode and the control gate electrode, which are identical in width to each other, are stacked with each other with no misalignment. In the split gate memory cell 701, on the other hand, a part of the control gate electrode 707 is arranged on the channel region 705 to form the selection gate 711. In the split gate memory cell 701, therefore, the area occupied by the element on the substrate 702 is increased by the selection gate 711 as compared with the stacked gate memory cell. In other words, it is difficult to highly integrate the split gate memory cell due to the aforementioned problems (2) and (3), although the same has no problem of overerasing.
(4) The memory cell array 802 employing the split gate memory cells 701 is complicated in structure and requires a long time for fabrication.
An object of the present invention is to provide a transistor capable of a high-speed operation and a semiconductor memory employing the same.
Another object of the present invention is to provide a method of fabricating a semiconductor memory capable of a high-speed operation.
Still another object of the present invention is to provide a transistor capable of a high-speed operation and high integration and a semiconductor memory employing the same.
A further object of the present invention is to provide a method of fabricating a semiconductor memory capable of a high-speed operation and high integration.
A further object of the present invention is to provide a semiconductor memory which causes no dispersion in write characteristics, has a high operating speed, can be refined, causes no overerasing, and can improve write and read characteristics, and a method of fabricating the same.
A transistor according to an aspect of the present invention comprises two cells having floating gate electrodes, respectively, and sharing a control gate electrode serving also as a selection gate electrode and an interconnection layer arranged above the floating gate electrodes of the two cells through an interlayer isolation film, and the control gate electrode is connected to the interconnection layer.
The transistor, having the two cells sharing the control gate electrode serving also as the selection gate electrode, can be highly integrated. The interconnection layer is arranged above the floating gate electrodes through the interlayer isolation film, whereby the capacitance between the interconnection layer and a substrate is reduced. Thus, signal delay on the interconnection layer is reduced to enable a high-speed operation.
The floating gate electrode of each cell is preferably opposed to the control gate electrode at one surface through an insulator film.
In this case, the floating gate electrode is opposed to the control gate electrode at one surface through the insulator film, whereby the opposition areas of the floating gate electrode and the control gate electrode are reduced as compared with those in the conventional transistor and the coupling capacitance between the floating gate electrode and the control gate electrode is reduced. Therefore, the potential of the floating gate electrode can be readily increased for injecting charges into the floating gate electrode at a high speed. Consequently, a high-speed write operation is enabled.
The floating gate electrode of each cell may have a projection on the side opposed to the control gate electrode.
In this case, charges can be efficiently extracted from the floating gate electrode of each cell, having the projection on the side opposed to the control gate electrode, to the control gate electrode.
The two cells may further include a common channel region and two impurity regions provided through the channel region so that the two floating gate electrodes are arranged on the channel region at a prescribed space through a first insulator film, the control gate electrode extends from above the channel region located between the two floating gate electrodes to above the two floating gate electrodes respectively through a second insulator film and the interconnection layer is arranged above the two impurity regions and the two floating gate electrodes through an interlayer isolation film.
The transistor, having the two floating gate electrodes sharing the control gate electrode, can be highly integrated. The part of the control gate electrode located on the channel region serves as the selection gate electrode, to cause no problem of overerasing.
The control gate electrode extends from above the channel region toward above the two floating gate electrodes and one side of each floating gate electrode is opposed to the control gate electrode, whereby the opposition areas of the floating gate electrode and the control gate electrode are reduced as compared with those in the conventional transistor and the coupling capacitance between the floating gate electrode and the control gate electrode is reduced. Therefore, the potential of the floating gate electrode can be readily increased for injecting charges from the channel region into the floating gate electrode at a high speed. Consequently, a high-speed write operation is enabled.
The interconnection layer is arranged above the floating gate electrodes through the interlayer isolation film, whereby the capacitance between the interconnection layer and the substrate is reduced. Thus, signal delay on the interconnection layer is reduced and a high-speed operation is enabled.
Charges may be injected from the channel region into one of the two floating gate electrodes by hot carriers in a write operation, while charges may be extracted from the two floating gate electrodes to the control gate electrode by tunnel currents in an erase operation.
In this case, the potential of each floating gate electrode can be readily increased due to the small coupling capacitance between the floating gate electrode and the control gate electrode, for enabling a high-speed write operation.
A semiconductor memory according to another aspect of the present invention comprises a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting with the first direction and a plurality of transistors connected between each pair of bit lines and arranged along each word line. Each transistor includes a channel region, two impurity regions provided through the channel region for partially forming the corresponding bit lines respectively, two floating gate electrodes arranged on the channel region at a prescribed space through a first insulator film and a control gate electrode extending from above the channel region located between the two floating gate electrodes to above the two floating gate electrodes respectively through a second insulator film. Each word line is arranged above the impurity regions and the floating gate electrodes of the corresponding plurality of transistors arranged along the first direction through an interlayer isolation film and connected to the control gate electrodes of the corresponding plurality of transistors.
The semiconductor memory, having the transistors each provided with the two floating gate electrodes sharing the control gate electrode, can be highly integrated. Further, a part of the control gate electrode located on the channel region serves as a selection transistor, to cause no problem of overerasing.
The control gate electrode of each transistor extends from above the channel region to above the two floating gate electrodes and one side of each floating gate electrode is opposed to the control gate electrode, whereby the opposition areas of the floating gate electrode and the control gate electrode are reduced as compared with those in the conventional semiconductor memory and the coupling capacitance between the floating gate electrode and the control gate electrode is reduced. Therefore, the potential of the floating gate electrode can be readily increased and for injecting charges from the channel region into the floating gate electrode at a high speed. Consequently, a high-speed write operation is enabled.
Further, each word line is arranged above the impurity regions and the floating gate electrodes of the transistors through the interlayer isolation film, whereby the capacitance between the word line and a substrate is reduced. Thus, signal delay on the word line is reduced and a high-speed operation is enabled.
The two floating gate electrodes of each transistor may have projections at least on the sides closer to the control gate electrode.
In this case, charges can be efficiently extracted from the floating gate electrodes of each transistor to the control gate electrode due to the projections provided on the sides of the floating gate electrodes closer to the control gate electrode. Therefore, an erase operation can be performed at a high speed.
Each transistor may share one of the two impurity regions with another transistor adjacent to one side thereof in the first direction while sharing the remaining one of the two impurity regions with still another transistor adjacent to the other side thereof in the first direction.
In this case, each adjacent pair of transistors share either impurity region, whereby the semiconductor memory can be highly integrated.
The semiconductor memory may further comprise a selection circuit for selecting one or more of the plurality of transistors and a potential set circuit for setting the potentials of the plurality of bit lines and the plurality of word lines so that charges are injected into one of the floating gate electrodes from the channel region of a transistor selected by the selection circuit by hot carriers in a write operation while setting the potentials of the plurality of bit lines and the plurality of word lines so that charges are extracted from one or both of the floating gate electrodes to the control gate electrode of a transistor selected by the selection circuit by a tunnel current in an erase operation.
A method of fabricating a semiconductor memory, including a plurality of transistors arranged in the form of a matrix in a first direction and a second direction intersecting with the first direction, according to still another aspect of the present invention comprises steps of forming a plurality of pairs of floating gate electrodes corresponding to the plurality of transistors on a semiconductor substrate along the first direction through a first insulator film, forming a plurality of impurity regions in portions of the semiconductor substrate between the floating gate electrodes of the transistors adjacent to each other in the first direction, forming a plurality of control gate electrodes corresponding to the plurality of transistors from above regions of the semiconductor substrate held between the pairs of floating gate electrodes to above the pairs of floating gate electrodes in the first direction through a second insulator film respectively, forming an interlayer isolation film on the plurality of impurity regions and the plurality of pairs of floating gate electrodes, and forming an interconnection layer for a plurality of word lines connected in common to the control gate electrodes of the plurality of transistors arranged in the first direction on the interlayer isolation film located on the plurality of impurity regions and the plurality of floating gate electrodes.
According to the inventive method, the semiconductor memory having the transistors each provided with the two floating gate electrodes sharing the control gate electrode can be highly integrated. A part of the control gate electrode located on the channel region serves as a selection transistor, to cause no problem of overerasing.
The control gate electrode of each transistor extends from above a region held between the pair of floating gate electrodes to above the floating gate electrodes while one side of each floating gate electrode is opposed to the control gate electrode, whereby the opposition areas of the floating gate electrode and the control gate electrode are reduced as compared with those in the conventional semiconductor memory and the coupling capacitance between the floating gate electrode and the control gate electrode is reduced. Therefore, the potential of the floating gate electrode can be readily increased for injecting charges from the channel region into the floating gate electrode at a high speed. Consequently, a high-speed write operation is enabled.
Further, the interconnection layer for the word lines is arranged above the plurality of impurity regions and the pairs of floating gate electrodes through the interlayer isolation film, whereby the capacitance between the word line and a substrate is reduced. Thus, signal delay on the word line is reduced and a high-speed operation is enabled.
The method may further comprise a step of forming projections on at least parts of opposed sides of each pair of floating gate electrodes.
In this case, the floating gate electrodes of each transistor have the projections on the sides opposed to the control gate electrode, whereby charges can be efficiently extracted from the floating gate electrodes to the control gate electrode.
The method may further comprise a step of reducing the thickness of the interlayer isolation film so that upper surfaces of the control gate electrodes of the plurality of transistors are exposed.
In this case, no contact holes may be formed in the interlayer isolation film for connecting the interconnection layer for the word lines to the plurality of control gate electrodes. Thus, the number of fabrication steps is reduced.
The method may further comprise steps of forming a mask on the interconnection layer for the plurality of word lines and successively patterning the interconnection layer for the plurality of word lines, the control gate electrodes and the floating gate electrodes through the mask.
Thus, the control gate electrodes and the floating gate electrodes can be formed in a self-alignment manner with respect to the word lines, whereby refinement can be enabled by reducing positioning allowance with no requirement for consideration of misalignment in lithography steps. Further, dispersion in coupling capacitance between the control gate electrodes and the floating gate electrodes is reduced. Thus, dispersion in characteristics is reduced and the element characteristics as well as the fabrication yield can be improved.
A transistor according to a further aspect of the present invention comprises a floating gate electrode, a control gate electrode serving also as a selection gate electrode and an interconnection layer arranged above the floating gate electrode through an interlayer isolation film, and the control gate electrode is connected to the interconnection layer.
In this transistor, the interconnection layer is arranged above the floating gate electrode through the interlayer isolation film, whereby the capacitance between the interconnection layer and a substrate is reduced. Thus, signal delay on the interconnection layer is reduced and a high-speed operation is enabled.
The floating gate electrode is preferably opposed to the control gate electrode at one surface through an insulator film.
In this case, the floating gate electrode is opposed to the control gate electrode at one surface through the insulator film, whereby the opposition areas of the floating gate electrode and the control gate electrode are reduced as compared in the conventional transistor and the coupling capacitance between the floating gate electrode and the control gate electrode is reduced. Thus, the potential of the floating gate electrode can be readily increased for injecting charges into the floating gate electrode at a high speed. Consequently, a high-speed write operation is enabled.
The floating gate electrode may have a projection on the side opposed to the control gate electrode. In this case, charges can be efficiently extracted from the floating gate electrode to the control gate electrode due to the projection provided on the side of the floating gate electrode opposed to the control gate electrode.
The transistor may further comprise a channel region and first and second impurity regions provided through the channel region so that the floating gate electrode is arranged on a side of the channel region closer to the first impurity region through a first insulator film, the control gate electrode extends from above a side of the channel region closer to the second impurity region to above the floating gate electrode through a second insulator film and the interconnection layer is arranged above the floating gate electrode through an interlayer isolation film.
In this case, the part of the control gate electrode located on the channel region serves as a selection gate electrode, to cause no problem of overerasing.
The control gate electrode extends from above the channel region to above the floating gate electrode and one side of the floating gate electrode is opposed to the control gate electrode, whereby the opposition areas of the floating gate electrode and the control gate electrode are reduced as compared in the conventional transistor and the coupling capacitance between the floating gate electrode and the control gate electrode is reduced. Therefore, the potential of the floating gate electrode can be readily increased for injecting charges from the channel region into the floating gate electrode at a high speed. Consequently, a high-speed write operation is enabled.
The interconnection layer is arranged above the floating gate electrode through the interlayer isolation film, whereby the capacitance between the interconnection layer and a substrate is reduced. Thus, signal delay on the interconnection layer is reduced and a high-speed operation is enabled.
A semiconductor memory according to a further aspect of the present invention comprises a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction intersecting with the first direction and a plurality of transistors provided at intersection points between the plurality of bit lines and the plurality of word lines. Each transistor includes a channel region, first and second impurity regions provided through the channel region, a floating gate electrode arranged on a side of the channel region closer to the first impurity region through a first insulator film and a control gate electrode extending from above a side of the channel region closer to the second impurity region to above the floating gate electrode through a second insulator film, and each word line is arranged above the floating gate electrodes of a plurality of corresponding transistors arranged along the second direction through an interlayer isolation film and connected to the control gate electrodes of the corresponding plurality of transistors.
In this semiconductor memory, a part of the control gate electrode located on each channel region serves as a selection transistor, to cause no problem of overerasing.
The control gate electrode of each transistor extends from above the channel region to above the floating gate electrode and one side of the floating gate electrode is opposed to the control gate electrode, whereby the opposition areas of the floating gate electrode and the control gate electrode are reduced as compared with those in the conventional semiconductor memory and the coupling capacitance between the floating gate electrode and the control gate electrode is reduced. Therefore, the potential of the floating gate electrode can be readily increased and for injecting charges from the channel region into the floating gate electrode at a high speed. Consequently, a high-speed write operation is enabled.
Each word line is arranged above the floating gate electrodes of the corresponding plurality of transistors arranged along the second direction through the interlayer isolation film, whereby the capacitance between the word line and a substrate is reduced. Thus, signal delay on the word line is reduced and a high-speed operation is enabled.
Each bit line may be connected to the second impurity regions of the corresponding plurality of transistors arranged along the first direction.
The floating gate electrode of each transistor is preferably opposed to the control gate electrode at one surface through an insulator film.
In this case, the floating gate is opposed to the control gate electrode at one surface through the insulator film, whereby the opposition areas of the floating gate electrode and the control gate electrode are reduced as compared with those in the conventional semiconductor memory and the coupling capacitance between the floating gate electrode and the control gate electrode is reduced. Therefore, the potential of the floating gate electrode can be readily increased for injecting charges into the floating gate electrode at a high speed. Consequently, a high-speed write operation is enabled.
The one surface of the floating gate electrode of each transistor may be the side surface closer to the first impurity region.
Each transistor may share the first impurity region with another transistor adjacent to one side thereof in the first direction while sharing the second impurity region with still another transistor adjacent to the other side thereof in the first direction.
In this case, each adjacent pair of transistors share either impurity region, whereby the semiconductor memory can be highly integrated.
The floating gate electrode of each transistor may have a projection on the side opposed to the control gate electrode.
In this case, charges can be effectively extracted from the floating gate electrode, having the projection on the side opposed to the control gate electrode, to the control gate electrode.
The semiconductor memory may further include a selection circuit for selecting one or more of the plurality of transistors and a potential set circuit for setting the potentials of the plurality of bit lines and the plurality of word lines so that charges are injected from the channel region of any transistor selected by the selection circuit into the floating gate electrode by hot carriers in a write operation while setting the potentials of the plurality of bit lines and the plurality of word lines so that charges are extracted from the floating gate electrode to the control gate electrode of any transistor selected by the selection circuit by a tunnel current in an erase operation.
A method of fabricating a semiconductor memory, including a plurality of transistors arranged in the form of a matrix in a first direction and a second direction intersecting with the first direction, according to a further aspect of the present invention comprises steps of forming a plurality of floating gate electrodes of the plurality of transistors on a semiconductor substrate along the first direction through a first insulator film, forming a plurality of control gate electrodes of the plurality of transistors from regions on the semiconductor substrate to above the floating gate electrodes in the first direction through a second insulator film respectively, forming a plurality of impurity regions of the plurality of transistors on portions of the semiconductor substrate located on both sides of the floating and control gate electrodes respectively, forming an interlayer isolation film on the semiconductor substrate and the plurality of floating gate electrodes, and forming interconnection layers for a plurality of word lines connected in common to a plurality of control gate electrodes of a plurality of transistors arranged in the second direction on the interlayer isolation film.
According to this method, a part of the control gate electrode located on each channel region serves as a selection transistor, to cause no problem of overerasing.
The control gate electrode of each transistor extends from above the semiconductor substrate to above the floating gate electrode and one side of the floating gate electrode is opposed to the control gate electrode, whereby the opposition areas of the floating gate electrode and the control gate electrode are reduced as compared with those in the conventional semiconductor memory and the coupling capacitance between the floating gate electrode and the control gate electrode is reduced. Therefore, the potential of the floating gate electrode can be readily increased for injecting charges from the channel region into the floating gate electrode at a high speed. Consequently, a high-speed write operation is enabled. The interconnection layers for the word lines are arranged on the interlayer isolation film along the second direction, whereby the capacitance between each word line and the substrate is reduced. Thus, signal delay on the word line is reduced, and a high-speed operation is enabled.
The method may further comprise a step of forming a projection on an edge portion of at least the side of the floating gate electrode of each transistor opposed to the control gate electrode.
In this case, the floating gate electrode of each transistor has the projection on the side opposed to the control gate electrode, whereby charges can be efficiently extracted from the floating gate electrode to the control gate electrode.
The method may further comprise a step of reducing the thickness of the interlayer isolation film so that upper surfaces of the control gate electrodes of the plurality of transistors are exposed.
In this case, no contact holes may be formed in the interlayer isolation film for connecting the interconnection layer for the word lines to the plurality of control gate electrodes. Thus, the number of fabrication steps is reduced.
A semiconductor memory according to a further aspect of the present invention comprises a semiconductor substrate, one or more control lines arranged above the semiconductor substrate, a plurality of impurity regions provided in the semiconductor substrate along the one or more control lines at a prescribed space, a plurality of channel regions provided on the semiconductor substrate between the plurality of impurity regions and a plurality of floating gate electrodes arranged on the plurality of channel regions, and the electrostatic capacitance between the control line on each channel region and the semiconductor substrate is set larger than that between the control line on each impurity region and the semiconductor substrate.
The electrostatic capacitance between each floating gate electrode and the semiconductor substrate may be set larger than that between each floating gate electrode and the control line.
Each of the one or more control lines may form a control gate electrode above each floating gate electrode while forming a selection gate electrode above each channel region.
Each of the one or more control lines may include a lower layer having non-conductivity on each impurity region while having conductivity on each channel region, and an upper layer, formed on the lower layer, having conductivity. The lower layer may be a conductor layer partially oxidized on each impurity region.
The semiconductor memory may further comprise a plurality of conductive block layers selectively formed on the plurality of impurity regions respectively and electrically connected with the plurality of impurity regions respectively, so that the plurality of floating gate electrodes are adjacent to the plurality of conductive block layers through a dielectric member.
Each of the one or more control lines may include a lower layer, separated into a plurality of parts, having conductivity, and an upper layer, formed on the lower layer, having conductivity, and a part of the lower layer located on each channel region may be electrically connected with the upper layer, while a part of the lower layer located on each impurity region may be isolated from the upper layer for forming the conductive block layer.
Each of the one or more control lines may have a width smaller than that of each floating gate electrode.
Each of the one or more control lines may have a first width on each channel region while having a second width smaller than the first width on each impurity region. The first width may be substantially equal to the width of each floating gate electrode, and the second width may be smaller than the width of each floating gate electrode.
Each floating gate electrode may have a sharp-angled projection on an upper edge portion opposed to the control line.
The plurality of floating gate electrodes may be arranged on each channel region at a prescribed space, and each of the one or more control lines may form a control gate electrode on the floating gate electrode located on each channel region while forming a selection gate electrode on the channel region located between the floating gate electrodes.
The one or more control lines may include a plurality of control lines, the plurality of impurity regions and the plurality of channel regions may be arranged in the form of a matrix along the direction of the plurality of control lines and a direction intersecting with the plurality of control lines, and the plurality of impurity regions arranged in the direction intersecting with the plurality of control lines may form bit lines respectively.
According to the present invention, a semiconductor memory which has no dispersion in write operation, can be refined, has a small problem of overerasing and can improve write and read characteristics by attaining optimization of the electrostatic capacitances in the channel region parts and those in the impurity region parts.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.